Circuitry for cancelling offsets of multiplexed color video signals

ABSTRACT

Offset cancelling circuitry for cancelling offsets among the reference levels of a plurality of video signals each being associated with a particular color. The video signals are each applied to a particular differential amplifier. A multiplexer and a sample and hold circuit multiplex the video signals so as to output the video signal through a single circuit. An analog-to-digital converter converts the multiplexed video signals to corresponding digital data. The color-by-color digital data are each averaged and the resulting mean values are used as correction data. Alternatively, the digital data from the analog-to-digital converter may be transformed to analog data and then fed back to the differential amplifiers as detected and integrated correction data. Further, the multiplexed video signals may be clamped by a clamp buffer circuit and fed back to the differential amplifiers. As a result, offsets among the video signals are cancelled via the sample and hold circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to offset cancelling circuitry forcorrecting deviations, or offsets, in reference level among a pluralityof video signals each being associated with a particular color and, moreparticularly, to offset cancelling circuitry advantageously applicableto a digital electronic still camera or similar video equipment.

2. Description of the Related Art

A digital electronic still camera or similar video equipment capable ofconverting an image to electric signals by, for example, solid stateimage sensors and storing them in a memory card is a recent achievementin the imaging art. The video signals to be applied from the imagesensors to processing circuitry may be implemented as analog red (R),green (G) and blue (B) color signals each being derived from aparticular color filter provided on an image pick-up cell array. The R,G and B signals are dot sequentially inputted to respective channels ofthe processing circuitry, subjected to level adjustment and othervarious kinds of signal processing including clamping, and thentransformed to digital data by an analog-to-digital converter (ADC).Since circuitry with a highly accurate ADC is expensive, it has beencustomary to sequentially convert the color signals to digital data by asingle line having a multiplexer and an ADC. The digital data aresubjected to various kinds of digital processing including gammacorrection and then written into a memory card. The gamma correctioncorrects a difference between the input characteristic of an image inputsystem and the display characteristic of a cathode ray tube or similardisplay device, as well known in the art. The gamma correction isexecuted by the equipment which shoots a scene. A gamma curverepresentative of a correction characteristic is such that theamplification factor or gamma gain is high in a range where the inputsignal of the equipment is low, i.e., in a low luminance range.

However, the problem with the conventional circuitry built in digitalelectronic still camera is that there occurs deviations or offsetsbetween the reference level and the R, G and B signals due toirregularities among the elements constituting the R, G and B channelsof the circuitry. Then, the R, G and B signals sharing a singlemultiplexer and a single ADC are digitized by the ADC without havingtheir offsets in reference level corrected and then the digitizedsignals undergo gamma correction. As a result, the offsets among thecolor signals are also amplified and superposed on the expected colorsignals as undesirable color deviation data. The color deviation data isespecially serious when it involves data lying in a comparatively lowluminance range where the gamma gain is high. As a result, an image witha low luminance cannot be accurately reproduced in respect of colors. Toeliminate this problem, offset adjustment is effected channel by channelsuch that the R, G and B signals match one another with respect to thereference level. However, the conventional offset adjustment should beextremely accurate and should not change over a long period of time.Moreover, such offset adjustment is done by hand.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide offsetcancelling circuitry which does not need manual adjustment of highaccuracy.

In accordance with the present invention, the offset cancelling circuitfor correcting a difference in reference level between a plurality ofvideo signals fed from an image pick-up circuit and each beingassociated with a particular color has a signal generating circuit forgenerating color separation pulses in synchronism with a reference clocksignal generated in the signal generating circuit and for generatingclamp pulses and clock pulses in synchronism with black-out periods ofthe video signals. A multiplexer multiplexes the video signals from theimage pick-up circuit in time serially in response to the colorseparation pulses from the signal generating circuit, and clamps thevideo signals in response to the clamp pulses from the signal generatingcircuit to thereby produce digital video signals via an ADC. A videosignal detecting circuit detects, in response to the clamp pulses fromthe signal generating circuit, the digital video signals of respectivecolors fed from the ADC. A mean value calculating circuits calculates amean value of clamp levels of the digital video signal detected by theassociated video signal detecting circuit, and sequentially selects themean values by a selector in response to the color separation pulsesfrom the signal generating circuit. A correcting circuit is responsiveto the video signals for correcting offsets of the video signals on thebasis of the mean values.

Also, in accordance with the present invention, offset cancellingcircuitry for correcting a difference in reference level between aplurality of video signals each being associated with a particular colorhas a plurality of amplifiers each being associated with a respectiveone of the video signals for correcting a DC level of the video signalin response to a DC voltage matching a control input. A multiplexersequentially selects and thereby multiplexes video signals amplified bythe amplifiers so as to output the video signals through a singlecircuit. A voltage source generates a reference voltage whichconstitutes a target for voltages of signals to be outputted by themultiplexer. A plurality of feedback paths are each associated with arespective one of the video signals for clamping the voltage of theassociated signal outputted by the multiplexer and not lying in a videoperiod, thereby applying a DC voltage matching a difference between thevoltage and the reference voltage to the control input of an associatedone of the plurality of amplifiers. A plurality of voltage storingdevices are each associated with a respective one of the video signalsfor storing the DC voltage until the next video signal of correspondingcolor arrives, and each applies the DC voltage to the control input ofan associated one of the amplifiers.

Further scope of applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications within the spirit and scope of the invention will becomeapparent to those skilled in the art from this detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and features of the present invention will become moreapparent from the consideration of the following detailed descriptiontaken in conjunction with the accompanying drawings, in which are givenby way of illustration only and thus are not limitative of the presentinvention, and wherein:

FIGS. 1A and 1B are block diagrams schematically showing, when combinedas shown in FIG. 1, a digital electronic still camera implemented withoffset cancelling circuitry embodying the present invention;

FIG. 1 shows a combination of FIGS. 1A and 1B;

FIGS. 2A-2H are timing charts showing various signals appearing in thecircuitry shown in FIGS. 1A and 1B;

FIGS. 3A and 3B are block diagrams schematically showing, when combinedas shown in FIG. 3, a digital electronic still camera implemented withan alternative embodiment of the present invention;

FIG. 3 shows a combination of FIGS. 3A and 3B;

FIGS. 4A-4H are timing charts showing various signals appearing in theembodiment of FIGS. 3A and 3B;

FIG. 5 is a block diagram schematically showing another alternativeembodiment of the present invention;

FIGS. 6A-6G are timing charts showing specific signals to be produced bya signal generating circuit included in the embodiment of FIG. 5; and

FIGS. 7A-7F are timing charts showing another set of specific signals tobe produced by the signal generating circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIGS. 1A and 1B of the drawings, a digital electronic stillcamera implemented with offset cancelling circuitry embodying thepresent invention is shown. As shown, the offset cancelling circuitry,generally 1, has an image pick-up circuit 12 for picking up an image andoutputting corresponding video signals in the form of R (red), G (green)and B (blue) signals. The, R, G and B signals are multiplexed by amultiplexer 14 and then transformed to digital data by ananalog-to-digital converter (ADC) 22. The digital data are routedthrough buses 110 and 112, detecting circuits 26R, 26G and 26B,integrating circuits 28R, 28G and 28B, a selector 30 and anadder/subtractor 32, whereby offset components contained in the digitaldata are cancelled data by data. As a result, the circuitry 1 producesR, G and B data containing substantially no offset components. The, R, Gand B data from the adder/subtractor 32 is subjected to gamma correctionby a gamma correction circuit 34, then subjected to, for example,digital image processing, and finally written into a memory card, notshown. It is to be noted that arrangements not directly relevant to thepresent invention although included in the camera are not shown ordescribed, and that the reference numerals attached to signalscorrespond to the those of the connection lines on which they appear.

A signal generating circuit 10 delivers to each section of the camera aparticular reference signal, not shown, in synchronism with a clocksignal generated therein. Particularly, the signal generating circuit 10produces color separation pulses SP_(R), SP_(G) and SP_(B) shown inFIGS. 2B-2D on outputs 90R, 90B and 90B thereof, respectively. Thesepulses SP_(R), SP_(G) and SP_(B) will be used to separate respectivelythe R signal representative of red, the G signal representative ofgreen, and the B signal representative of blue. Further, the signalgenerating circuit 10 generates on an output 92 thereof a clamp pulseCP, FIG. 2A, which remains in a high level during the black-out periodof the video signals, while generating a clock pulse CK on an output 92.

The image pick-up circuit 12 has CCD (Charge Coupled Device) imagesensors, not shown, and transforms an image incident on thelight-sensitive surface of each image sensor via an associated colorfilter into an electric signal. Specifically, the image pick-up circuit12 generates a transfer clock signal in response to a particularreference signal from the signal generating circuit 10 and feeds it tothe CCD image sensors for driving them. Also, the circuit 12 reads R, Gand B signals each being associated with a particular color filter outof the CCD image sensors, amplifies them, and then delivers theresulting R, G and B signals from outputs 100R, 100G and 100B thereof tothe multiplexer 14 in parallel.

The multiplexer 14 receives the parallel R, G and B signals from theimage pick-up circuit 12 at the inputs 100R, 100G and 100B thereof,respectively. In response to the color separation pulses SP_(R), SP_(G)and SP_(B) from the signal generating circuit 10, the multiplexer 14sequentially selects the R, G and B signals so as to multiplex them timeserially, i.e., on the same time axis. The multiplexed R, G and Bsignals appear on an output 102 which is connected to a buffer 18 andconnected to ground via a capacitor 16. The multiplexer 14, capacitor 16and buffer 18 cooperate as a sample and hold circuit. Specifically, themultiplexer 14 sequentially samples the R, G and B signals in responseto the color separation pulses SP_(R), SP_(G) and SP_(B), the capacitor16 holds the sampled signals, and the buffer 18 outputs them. The output104 of the buffer 18 is connected to the clamp circuit 20.

The clamp circuit 20 clamps the R, G and B signals fed from the output104 of the buffer 18 and multiplexed time serially. Connected to the ADC22 via an output 106, the clamp circuit 20 has a function of clampingthe R, G and B signals in response to a clamp pulse CP fed from thesignal generating circuit 10 during the black-out period of the R, G andB signals. Another function of the clamp circuit 20 is to shift thepedestal levels of the signals inputted thereto during the clamp periodto match them to the input range of the ADC 22.

The ADC 22 converts the voltages of the R, G and B signals from theinput 106 to digital data. Specifically, the ADC 22 samples andquantizes the R, G and B signals in response to a clock pulse CK fromthe signal generating circuit 10 to thereby generate, for example,10-bit digital data. The 10-bit digital data are outputted as R, G and Bdata each having one of 1,024 quantizing levels. The digital R, G and Bdata are sequentially applied to the adder/subtractor 32, FIG. 1B, overthe bus 110. The bus 112 which is, for example, the lower four bits ofthe bus 110 branches off the bus 110 and extends to the detectingcircuits 26R, 26G and 26B, FIG. 1B. The detecting circuit 26R detectsthe R data out of the R, G and B data appearing on the bus 112.Specifically, this circuit 26R has a function of outputting, whensupplied with both the clamp pulse CP and the color separation pulseSP_(R) from the signal generating circuit 10, the data on the bus 112 toa 4-bit output bus 114R, i.e., a gating function. More specifically, thecircuit 26R detects the R data during the clamp period and transfers itto the integrating circuit 28R over the bus 114R. Likewise, thedetecting circuits 26G and 26B detect respectively the G data and B datain response to the color separation pulses SP_(G) and SP_(B) andtransfers them to the associated integrating circuits 28G and 28B.

The integrating circuit 28R adds up the R data sequentially fed from thedetecting circuit 26R so as to generate mean data representative of amean value thereof. Specifically, the integrating circuit 28R has afunction of adding up the R data applied thereto via the input bus 114Rduring the clamp period, a function of producing a mean of the R data,and a function of continuously transferring the mean data to theselector 30 over a 4-bit output bus 116R as correction data until theclamp pulse CP arrives. Likewise, the integrating circuits 28G and 28Bgenerate respectively G data and B data in response to the colorseparation pulses SP_(G) and SP_(B) and transfers them to the selector30 over respective output buses 116G and 116B.

The selector 30 sequentially connects the input buses 116R, 116G and116B to a 4-bit output bus 118 thereof in response to the colorseparation pulses SP_(R), SP_(G) and SP_(B) fed from the signalgenerating circuit 10. The output bus 118 is connected to theadder/subtractor 32. Connecting the input buses 110 and 118, theadder/subtractor 32 arithmetically processes the data arrived over thebuses 110 and 118 and then outputs the resulting data on an output bus120 thereof. Specifically, the adder/subtractor 32 subtracts one of the10-bit data from the bus 110 and the 4-bit correction data from the bus118 from the other while synchronizing them to each other. In thismanner, the data are digitally processed to correct offsets of the R, Gand B signals by the correction data, i.e., the mean values of referencelevel. This allows the gamma correction circuit 34 connected to theoutput bus 120 to execute processing stably.

The gamma correction circuit 34 compensates for a difference between theinput characteristic of the image pick-up system and the displaycharacteristic of a cathode ray tube or similar display device.Specifically, as the output data of the adder/subtractor 32 is appliedto the input bus 120, the gamma correction circuit 34 executes accurategamma correction with the data. The data undergone gamma correction isfed out via an output bus 122, subjected to various kinds of signalprocessing, and finally written to a memory card, not shown.

The operation of the offset cancelling circuitry 1 will be describedwith reference to FIGS. 2A-2H which shows various signals appearingduring the black-out period of the video signals. First, when the camerawith the circuitry 1 is in operation with a power switch, not shown,thereof turned on, the signal generating circuit 10 produces the colorseparation pulses SP_(R), SP_(G) and SP_(B) on the outputs 90R, 90G and90B, respectively. At the same time, the signal generating circuit 10produces the clamp pulse CP on the output 92 and the clock pulse CK onthe output 94.

The image pick-up circuit 12 transforms an image focused onto thelight-sensitive surfaces of the CCD image sensors via associated colorfilters to electric signals and delivers the resulting R, G and Bsignals via the outputs 100R, 100G and 100B, respectively. The R, G andB signals are sequentially selected by the multiplexer 14 in response tothe color separation signals SP_(R), SP_(G) and SP_(B) shown in FIGS.2B-2D. As a result, the R, G and B signals are multiplexed by themultiplexer 14 on the same time axis, as shown in FIG. 2E specifically,while each being held by the capacitor 16 and buffer 18 for apredetermined period of time. In FIG. 2E, the R, G and B signals areshown as sequentially appearing in this order. The multiplexed, R, G andB signals are applied to the input circuit of the clamp circuit 20. Inresponse, the clamp circuit 20 clamps the R, G and B signals by using,for example, the level indicated by a dashed line in FIG. 2E as a clamplevel.

The clamp circuit 20 delivers the R, G and B signals to the ADC 22 insuch a manner that the clamp level of the signals coincides with, forexample, the zero input level of the ADC 22. The ADC 22 sequentiallyconverts the R, G and B signals to digital data and produces theresulting digital R, G and B data on the output 110 in parallel. The R,G and B data are transferred from the ADC 22 to the adder/subtractor 32.At the same time, the lower four bits of the R, G and B data are appliedto the detecting circuits 26R, 26G and 26B over the input bus 112. Whenboth the clamp pulse CP and the color separation pulse SP_(R), SP_(G) orSP_(B) become significant, the detecting circuit 26R, 26G or 26B outputsthe associated color data. For example, the detecting circuit 26Rdetects, among the data appearing on the input bus 112, the R data whenboth the clamp pulse CP and the color separation pulse SP_(R) arereceived, delivering the R data via the output bus 114R as 4-bit digitaldata. As a result, the R data sequentially appear on the output bus 114Rin synchronism with the color separation pulses SPR, as shown in FIG.2F. In FIG. 2F, the R data are represented by 4-bit 16-step data by wayof example. The lower four bits of the G data and the lower four bits ofthe B data are sequentially delivered over the output buses 114G and114B, respectively.

The data from the detecting circuits 26R, 26G and 26B are applied to theinput buses 114R, 114G and 114B of the integrating circuits 28R, 28G and28B, respectively. The integrating circuits 28R, 28G and 28B each addsup the input data over the clamp period so as to produce a mean valuethereof. For example, as shown in FIG. 2G, the integrating circuit 28Rproduces a mean value of the R data while delivering it over the outputbus 116R as correction data, until the next clamp pulse CP arrives.Likewise, the lower four bits of the G data and the lower four bits ofthe B data are respectively delivered over the output buses 116G and116B as correction data. The data from the output buses 116R, 116G and116B are applied to the selector 30.

The selector 30 sequentially selects the data on the buses 116R, 116Gand 116B in response to the color separation pulses SP_(R), SP_(G) andSP_(B) fed from the signal generating circuit 10 while transferring thecorrection data R, G and B to the adder/subtractor 32 over the outputbus 118. Also transferred to the adder/subtractor 32 over the input bus110 are the 10-bit R, G and B data. Hence, the adder/subtractor 32subtracts each of the correction data R, G and B from associated ones ofthe R, G and B data and sequentially produces the resulting residuals onthe output bus 120. As a result, during the clamp period, the output bus120 of the adder/subtractor 32 remains at a constant level due to thecancellation of the offsets of the color data, as shown in FIG. 2H. Thecorrection data of the respective colors are also sequentiallysubtracted from video data transferred after the black-out period, theresulting residuals appearing on the output bus 120. Consequently, theadder/subtractor 32 produces data containing substantially no offsetcomponents on the output bus 120.

The offset-free data from the adder/subtractor 32 are applied to theinput bus 120 of the gamma correction circuit 34 and subjected toaccurate gamma correction on the basis of a correction curve for digitalgamma correction. The corrected data are written to a memory card, notshown, after various kinds of signal processing.

A reference will be made to FIGS. 3A, 3B and 4 for describing analternative embodiment of the present invention which is also applied toa digital electronic still camera. The constituents of this embodimentwhich are identical with or similar to those of the previous embodimentare designated by the same reference numerals, and a detaileddescription will not be made to avoid redundancy. As shown, offsetcancelling circuitry 2, like the circuitry 1 shown in FIGS. 1A and 1B,produces offset-free R, G and B data from the R, G and B signalsgenerated by the image pick-up circuit 12. The signal generating circuit10, image pick-up circuit 12, multiplexer 14, clamp circuit 20, ADC 22and gamma correction circuit 34 shown in FIG. 3A and 3B may beconstructed in the same manner as those of FIG. 1A and 1B. Thedifference is that this embodiment additionally includes feedback clampcircuits for feeding back the lower four bits of the output data of theADC 22 to the input side. Specifically, the offset cancelling circuitry2 further comprises a buffer 38, differential amplifiers 40R, 40G and40B, detecting and integrating circuits 42R, 42G and 42B, correctiondata generating circuits 44R, 44G and 44B, digital-to-analog converters(DACs) 46R, 46G and 46B, resistors 48R, 48G and 48B and capacitors 50R,50G and 50B, as illustrated.

In detail, the outputs 100R, 100G and 100B of the image pick-up circuit12 are connected to the noninverting inputs (+) of the differentialamplifiers 40R, 40G and 40B, respectively, which are fed with invertinginputs (-) 130R, 130G and 130B. The differential amplifiers 40R, 40G and40B each produce an output representative of a difference between thesignal applied to the noninverting input and a signal applied to theinverting input (-). The outputs 132R, 132G and 132B of the differentialamplifiers 40R, 40G and 40B, respectively, are connected to themultiplexer 14 whose output 134 is in turn connected to the clampcircuit 20. The output 136 of the clamp circuit 20 is connected to thebuffer 38. The buffer 38 plays the role of a preamplifier for amplifyingthe output signal of the clamp circuit 20, i.e., for producing adequateR, G and B signals matching the ADC 22 connected to the output 138thereof. The ADC 22 is connected to the gamma correction circuit 34 by a10-bit bus 140. A bus 142 branches off the bus 140 and extends to thedetecting and integrating circuits 42R, 42G and 42B, FIG. 3B. The bus142 is representative of the lower four bits of the output signal of theADC 22.

The detecting and integrating circuit 42R detects R data out of the R, Gand B data appearing on the bus 142, adds up the consecutive R data, andthen produces mean data representative of a mean value of the R data.Specifically, this circuit 42R detects R data appearing during the clampperiod in response to the clamp pulse CP and color separation pulsesSP_(R) from the signal generating circuit 10, thereby outputting themean data. The circuit 42R may be implemented as a combination of thedetecting circuit 26R and integrating circuit 28R shown in FIG. 1B. Themean data of the R data is fed from the circuit 42R to the correctiondata generating circuit 44R connected to the output bus 144R of thecircuit 42R. Likewise, the detecting and integrating circuits 42G and42B detect respectively G data and B data in response to the colorseparation pulses SP_(G) and SP_(B), produce mean data of the respectivecolor data, and then deliver them to the associated correction datagenerating circuits 44G and 44B.

The correction data generating circuit 44R generates data for correctingan offset on the basis of the mean data from the detecting andintegrating circuit 42R. Specifically, on receiving the mean dataincluding an offset on the input bus 144R, the circuit 44R generates4-bit correction data to provide the mean data with a predeterminedreference value and then transfers the correction data to the DAC 46Rwhich is connected to an output bus 146R. Likewise, the correction datagenerating circuits 44G and 44B generate correction data associated withG data and B data, respectively.

The DAC 46R converts the correction data of four bits from thecorrection data generating circuit 44R to an analog voltage in responseto the clock CK from the signal generating circuit 10, the analogvoltage appearing on an output bus 148R. The output bus 148R isconnected to the inverting input 130R of the differential amplifier 40Rvia the resistor 48R. The inverting input 130R is connected to groundvia the capacitor 50R. The capacitor 50R, therefore, accumulates andmemorizes the voltage applied to the terminal 130R. The detecting andintegrating circuit 42R, correction data generating circuit 44R, DAC 46Rand resistor 48R constitute a feedback path to the differentialamplifier 40 in combination. In this configuration, as the voltagestored in the capacitor 50R rises, the potential difference between thetwo inputs to the differential amplifier 40R is reduced in a relativesense to in turn lower the signal level on the output 132R of theamplifier 40R. Conversely, on the fall of the voltage stored in thecapacitor 50R, the potential difference between the inputs to thedifferential amplifier 40R and, therefore, the signal level on theoutput 132R is increased in a relative sense. In this manner, a feedbackclamp circuit is implemented which generates correction data from thelower 4-bit data produced by the ADC 22, transforms the correction datato an analog voltage, stores the analog voltage in the capacitor 50R,and then negatively feeds it back to the differential amplifier 40R.Likewise, the DACs 46G and 46R, resistors 48G and 48B and capacitors 50Gand 50B cooperate to generate correction voltages associated with G dataand B data, respectively.

The operation of the illustrative embodiment will be described withreference to FIGS. 4A-4H which show the various signals appearing duringthe black-out period of the video signals. First, when the camera withthe circuitry 2 is in operation, the signal generating circuit 10produces the color separation pulses SP_(R), SP_(G) and SP_(B) on theoutputs 90R, 90G and 90B, respectively, as shown in FIGS. 4C-4E. At thesame time, the signal generating circuit 10 produces the clamp pulse CP,FIG. 4A, on the output 92 and the clock pulse CK on the output bus 94.

The image pick-up circuit 12 transforms an image focused onto thelight-sensitive surfaces of the CCD image sensors via associated colorfilters to electric signals and delivers the resulting R, G and Bsignals to the noninverting inputs 100R, 100G and 100B of thedifferential amplifiers 40R, 40G and 40B, respectively. Signals to beapplied to the inverting inputs 130R-130B of the differential amplifiers40R-40B are generated by the following procedure.

First, the differential amplifiers 40R, 40G and 40B produce respectivelyoutputs representative of differences between the R, G and B signalsdelivered to the noninverting inputs (+) 100R, 100G and 100B and thevoltages applied to the inverting inputs (-) 130R, 130G and 130B ontheir outputs 132R, 132G and 132B. The multiplexer 14 multiplexes theoutputs of the differential amplifiers 40R-40B time serially to producea signal in which the R, G and B signals appear one after another andoutput through a single circuit 134. The R, G and B signals aresequentially fed to the clamp circuit 20 via the output circuit 134 ofthe multiplexer 14 and then to the buffer 38. As a result, a signalshown in FIG. 4B is generated in which the R, G and B signalssequentially appear and to which a predetermined DC voltage is added tomatch it to the predetermined input level of the ADC 22. The R, G and Bsignals are applied to the input 138 of the ADC 22 to be converted to10-bit digital data. The lower four bits of the 10-bit data aretransferred to the detecting and integrating circuits 42R, 42G and 42Bover the bus 142.

The detecting and integrating circuit 42R, for example, selects the Rdata out of the 4-bit R, G and B data appearing on the input bus 142 inresponse to the clamp pulse CP and color separation pulse SP_(R). The Rdata appears on the input bus 142 every time the color separation pulseSP_(R) arrives at the detecting and integrating circuit 42R, as shown inFIG. 4F in the form of steps representative of digital numerical values.The circuit 42R adds up the R data appearing in the clamp period inresponse to every color separation pulse SP_(R) and then produces a meanvalue thereof. The mean value or mean data continuously appears on theoutput 144R of the circuit 42R over a predetermined period of time untilthe next clamp pulse CP arrives, as indicated by a dashed line in FIG.4G by way of example.

On receiving the mean data, the correction data generating circuit 44Rgenerates correction data such that the R data sequentially arrivingduring the clamp period have a predetermined reference level, as shownin FIG. 4G by way of example. The correction data is fed to the input146R of the DAC 46R via the output 146R of the correction datagenerating circuit 44R. The DAC 46R converts the correction data to ananalog voltage and then delivers the voltage to the capacitor 50R viathe resistor 48R, thereby charging the capacitor 50R. At this instant,the charging voltage is fed back to the inverting input 130R of thedifferential amplifier 40R forming a feedback loop. Likewise, thedetecting and integrating circuits 42G and 42B detect respectively the Gdata and B data out of the R,G and B data and produce mean data thereof.The correction data generating circuits 44G and 44B generate correctiondata on the basis of the G data and B data, respectively. The correctiondata from these circuits 44G and 44B are each converted to an analogcorrection voltage and then applied to the associated capacitor 50G or50B via the resistor 48G or 48B while being fed back to the differentialamplifier 40G or 40B.

The differential amplifiers 40R, 40G and 40B produce respectively thedifferences between the correction voltages applied to the invertinginputs 130R, 130G and 130B and the R, G and B signals applied to thenoninverting inputs 100R, 100G and 100B and then amplify them. As aresult, the signal voltages appearing on the outputs 132R, 132G and 132Bof the differential amplifiers 40R, 40G and 40B each has a constantlevel. These voltages are multiplexed by the multiplexer 14, clamped bythe clamp circuit 20, and then applied to the buffer 38 through thesingle circuit 136. After the R, G and B signals have been amplified bythe buffer 38, they are converted to digital data by the ADC 22. Theresulting output of the ADC 22 is shown in FIG. 4H.

As stated above, the R, G and B signals are respectively applied to thenoninverting inputs 100R, 100G and 100B of the differential amplifiers40R, 40G and 40B during a clamp period. The clamp levels of the R, G andB signals during the black-out period are each corrected to apredetermined level by a correction voltage generated color by color andapplied to the associated inverting input 130R, 130G or 130B. Thecorrection voltages are stored in the associated capacitors 50R, 50G and50B until the clamp period of the next blackout period. After thisclamping period, R, G and B signals representative of an image areapplied from the image pick-up circuit 12 to the noninverting inputs100R, 100G and 100B while correction voltages stored in the capacitors50R, 50G and 50B are applied to the inverting inputs 130R, 130G and130B. This cancels offsets among the R, G and B signals which willappear on the outputs 132R, 132G and 132B of the differential amplifiers40R, 40G and 40B, respectively. Therefore, the resulting color signalson the outputs 132R, 132G and 132B are substantially identical inrespect of an offset component. These color signals are multiplexed bythe multiplexer 14, clamped by the clamp circuit 20, provided with a DCcomponent so as to be outputted through the single circuit formed by thecircuits 134, 136 and 138, and then amplified by the buffer 38. The R, Gand B signals from the buffer 38 are converted to 10-bit digital data bythe ADC 22 and then transferred to the gamma correction circuit 34. Thisis followed by the same procedure as in the embodiment shown in FIGS.1A, 1B and 2. At this instant, although the lower four bits of colordata are applied to the detecting and integrating circuits 42R-42B overthe bus 142, the circuits 42R-42B do not detect the color data since theclamp pulse CP are not applied thereto. This particular embodimenteffectively uses the input range or dynamic range of the ADC 22 sincethe input to the ADC 22 is free from offsets.

Referring to FIG. 5, another alternative embodiment of the presentinvention will be described which is also applied to a digitalelectronic still camera. In this embodiment, the same or similarconstituents as or to the previous embodiments are designated by thesame reference numerals, and a detailed description will not be made toavoid redundancy. As shown, offset cancelling circuitry, generally 3,has a sample and hold circuit 216 for multiplexing R, G and B signalsfed from the image pick-up circuit 12, and an ADC 218 to which theresulting R, G and B signals are applied through a single circuit 206time serially. Differential amplifiers 214R, 214G, 214B, 222R, 222G and222B, switches 226R, 226G and 226B, capacitors 28R, 28G and 28B andbuffers 230R, 230G and 230B constitute feedback clamp circuits forproducing offset-free multiplexed R, G and B signals. There are alsoshown in the figure the signal generating circuit 10, gamma correctioncircuit 34, and a reference voltage source 24. It is to be noted that R,G and B stand for red data, green data, and blue data, respectively.

The signal generating circuit 10 delivers to each section of the cameraa particular reference signal, not shown, in synchronism with a clockbuilt therein. As shown in FIGS. 6A-6G, the circuit 10 generates a clampsignal CP which goes high in synchronism with a clamp period 50 includedin one horizontal scanning period or 1H period of the video signals.Particularly, as shown in FIGS. 6A-6D, the circuit 10 sequentiallyproduces clamp signals CP_(R), CP_(G) and C_(P) on outputs 92R, 92B and92B thereof, respectively. Since the embodiment deals with three primarycolor signals, i.e., R, G and B signals, the clamping periods 50R, 50Gand 50B each goes high every 3H period of the video signals. Further, asshown in FIGS. 6E-6G, the circuit 10 sequentially generates colorseparation signals SP_(R), SP_(G) and SP_(B) in the video period 52 ofthe video signals on outputs 90R, 90G and 90B thereof, respectively. Thecolor separation signals SP_(R), SP_(G) and SP_(B) separate respectivelyan R signal, a G signal and a B signal representative of red, green andblue. Specifically, the circuit 10 generates these signals SP_(R),SP_(G) and SP_(B) such that when the clamp signal CP of correspondingcolor appears in, among others, the clamp period 50, each of them goeshigh during the clamp period of the color signal, e.g., in synchronismwith the clamp period 50R while remaining in a low level in the otherclamp periods 50G and 50B.

The image pick-up circuit 12 has CCD image sensors, not shown, andtransforms an image incident on the photosensitive surface of each imagesensor via an associated color filter into an electric signal.Specifically, this circuit 12 generates a transfer clock signal inresponse to a particular reference signal from the signal generatingcircuit 10 and feeds it to the CCD image sensors for driving them. Also,the circuit 12 reads R, G and B signals each being associated with aparticular color filter out of the CCD image sensors, amplifies them,and then delivers the resulting R, G and B signals from outputs 100R,100G and 100B thereof in parallel. The outputs 100R, 100G and 100B areconnected to the noninverting inputs of differential amplifiers 214R,214G and 214B, respectively.

The differential amplifier 214R amplifies a difference between the Rsignal applied to the noninverting input 100R and a signal applied to aninverting input 102R. The resulting output of the differential amplifier214R is fed to a sample and hold circuit 216. The differentialamplifiers 214G and 214B are identical in construction with thedifferential amplifier 214R and respectively connected to the outputs100G and 100B of the image pick-up circuit 12. The outputs 104G and 104Bof the differential amplifiers 214G and 214B are also connected to thesample and hold circuit 216.

The sample and hold circuit 216 has switches 32R, 32G and 32Bconstituting a multiplexer in combination with a capacitor 234, and anamplifier 36. This circuit samples the signals applied to the inputs104R, 104G and 104B thereof and holds a voltage on an output 108, for apredetermined period of time. Specifically, the switches 32R, 32G and32B are respectively opened and closed by the color separation signalsSP_(R), SP_(G) and SP_(B) fed from the signal generating circuit 10,thereby producing a multiplexed output for one line circuit. Forexample, the switch 32R has the contacts thereof repetitively connectedby the color separation signals SP_(R) sequentially applied thereto,gating the R signal on the input 100R. Likewise, the switches 32G and32B gate respectively the G and B signals in response to the colorseparation signals SP_(G) and SP_(B). As a result, the switches 32R, 32Gand 32B play the role of a multiplexer for producing the multiplexed R,G and B signals on an output 108. The output 108 of the multiplexer isconnected to the amplifier 36 and also to ground via the capacitor 234which holds a potential for a moment. The sample and hold circuit 216made up of the multiplexer, i.e., switches 32R-32B, capacitor 234 andamplifier 36 as stated above, sequentially samples the color signals inresponse to the color separation signals SP_(R), SP_(G) and SP_(B),holds the sampled color signals by the capacitor 234, and then deliversthem via the output 206 of the amplifier 36. The output 206 is connectedto differential amplifiers 222R, 222G and 222B and to an ADC 218 aswell.

The differential amplifier 222R has an inverting input 208 connected toa reference voltage source 24 which generates a reference voltage VR,i.e., a target voltage for the output 206 of the sample and hold circuit216. The differential amplifier 222R compares the voltage of the signalapplied to the noninverting input 206 thereof with the reference voltageVR and produces a signal representative of the resulting reference on anoutput 110R thereof. The output 110R is connected to a switch 226R. Theswitch 226R opens and closes in response to the clamp signals CP_(R)sequentially fed from the signal generating circuit 10. The switch 226Rhas an output terminal 112R connected to a buffer 230R and also toground via a clamp capacitor 28R. The clamp capacitor 28R stores thevoltage applied to the terminal 112R and holds it over the 3H period ofthe video signals. The buffer 230R amplifies the signal on the input112R to generate a correction voltage and then produces it on an output102R.

The differential amplifier 222R, switch 226R, capacitor 28R, buffer 230Rand differential amplifier 214R form a feedback path terminating at thesample and hold circuit 216. In this configuration, the voltagerepresentative of the difference between the voltage applied to thenoninverting input 206 of the differential amplifier 222R and thereference voltage VR is applied to and stored in the clamp capacitor28R. As the voltage of the clamp capacitor 28R rises, the differencebetween the two inputs of the differential amplifier 214R decreases in arelative sense to lower the level on the output 104R of the amplifier214R. Conversely, on the fall of the voltage of the clamp capacitor 28R,the difference between the inputs of the amplifier 214R increases in arelative sense so as to raise the level on the output 104R. This part ofthe circuitry, therefore, constitutes a feedback clamp circuit for the Rsignal. The voltage of the R signal during the clamp period appears onthe output 206 of the sample and hold circuit 216 and coincides with thetarget voltage VR.

A feedback clamp circuit identical with the above-described feedbackclamp circuit is also assigned to each of the G and B signals.Specifically, differential amplifiers 222G and 222 B, switches 226G and226B, capacitors 28G and 28B and buffers 230B and 230G clamprespectively the G and B signals in response to the color separationsignals SP_(G) and SP_(B), delivering the resulting outputs to theassociated differential amplifiers 214G and 214B via outputs 102G and102B.

The ADC 218 samples, in response to the reference signal from the signalgenerating circuit 10, the voltage applied to the input 206 thereof andquantizes the sampled voltage to generate, for example 10-bit digitaldata. The digital data is applied to the gamma correction circuit 34over a bus 114. The gamma correction circuit 34 compensates for thedifference between the input characteristic of the image pick-up systemand the display characteristic of, for example, a cathode ray tube.Specifically, receiving the digital data free from color signal offsetsover the bus 4, the circuit 34 subjects the data to accurate gammacorrection. The corrected data from the circuit 34 is fed out over anoutput bus 122, subjected to various kinds of signal processing, andthen written to a memory card, not shown.

A reference will be made to FIGS. 6A-6G for describing a specificoperation of the this embodiment. As shown, when the camera with thecircuitry 3 is in operation, the signal generating circuit 10 producescolor separation signals SP_(R), SP_(G) and SP_(B) on the outputs 90R,90G and 90B, respectively, and produces clamp signals CP_(R), CP_(G) andCP_(B) on the outputs 92R, 92G and 92B, respectively. As an image isfocused onto the CCD image sensors of the image pick-up circuit 12 viathe associated color filters, the image sensors convert it into electricsignals. As a result, R, G and B signals are respectively fed from theoutputs 100R, 100G and 100B of the image pick-up circuit 12 to thenoninverting inputs 100R, 100G and 100B of the differential amplifiers214R, 214G and 214B. How the signals to be applied to the invertinginputs of the differential amplifiers 214R-214B are generated will bedescribed, taking the signal to the inverting input 102R as an example.

As shown in FIG. 6B, during the first clamp period 50R of the R signal,the differential amplifier 214R produces a voltage representative of adifference between the R signal on the noninverting input 100R and thevoltage on the inverting input 102R. This voltage is applied to theswitch 32R of the sample and hold circuit 216 via the output 104R of thedifferential amplifier 214R. In response to the color separation signalSP_(R), the switch 32R remains turned on during the clamp period 50Rwith the result that the signal from the differential amplifier 214R istemporarily stored in the capacitor 234. The voltage stored in thecapacitor 234 is amplified by the amplifier 36 and then fed to the ADC218 and the noninverting input of the differential amplifier 222R viathe output 206. The differential amplifier 222R compares the voltage onthe inverting input thereof with the reference voltage VR from thereference voltage source 24, amplifies their difference, and thenproduces it on the output 110R. The signal from the amplifier 222R isstored in the clamp capacitor 28R via the switch 226R which has beenclosed by the clamping signal CP.sub. R. The clamp capacitor 28R holdsthe voltage over a 3H period shown in FIG. 6A. The voltage stored in theclamp capacitor 28R is fed to the buffer 230R and amplified to apredetermined level thereby. This amplified voltage is applied from theoutput 102R of the buffer 230R to the inverting input 102 of thedifferential amplifier 214R as a correction voltage.

The differential amplifier 214R amplifies a difference between thecorrection voltage applied to the inverting input 102R by the aboveprocedure and the R signal fed from the image pick-up circuit 12. Inthis manner, the R signal is clamped during the clamp period 50R so asto produce a correction voltage, amplified on the basis of thecorrection voltage, and then delivered via the output 104R. Since theoutput of the differential amplifier 222R is stored in the clampcapacitor 28R over the 3 H period, amplified by the buffer 230R, andthen fed to the inverting input 102R of the differential amplifier 214R,the difference between the R signal and the correction voltage iscontinuously amplified even after the clamp period 50R. During the nextclamp period 50G, the switches 32G and 226G are turned on to generate acorrection voltage for the G signal. Further, during the clamp period50B which follows the period 50G, the switches 32B and 226B are turnedon to generate a correction voltage for the B signal. These correctionsignals are applied to the inverting inputs 102G and 102B of theassociated differential amplifiers 214G and 214B. The G signal and Bsignal are amplified thereby respectively by differential amplifiers214G and 214B on the basis of the correction voltages and then deliveredon the outputs 104G and 104B. The resulting R, G and B signals from thedifferential amplifiers 214R, 214G and 214B are substantially of thesame level due to the correction of their offsets.

During a video period 52 which follows the clamp period 50R, R, G and Bsignals are fed from the image pick-up circuit 12 to the noninvertinginputs 100R, 100G and 100B of the differential amplifiers 214R, 214G and214B, respectively. Then, the R, G and B signals are each amplified by aparticular correction voltage appearing on the associated invertinginput 102R, 102G or 102B. The R signal amplified by the differentialamplifier 214R appears on the output 104R first. At this time, theswitch 32R of the sample and hold circuit 216 is turned on by the colorseparation signal SP_(R) _(R). As a result, the voltage of the R signalis stored in the capacitor 234 via the output 108 of the switch 32R. Thevoltage temporarily held in the capacitor 234 is amplified by theamplifier 36 and then fed out via the output 206. Subsequently, the Rsignal from the sample and hold circuit 216 is converted to 10-bitdigital data by the ADC 218 and then applied to the gamma correctioncircuit 34 in parallel over the bus 114. At this instant, although thesignal from the sample and hold circuit 216 is also applied to thenoninverting input 206 of the differential amplifier 222R and producedon the output 110R of the amplifier 222R, the switch 226R is not turnedon since the clamp signal CP_(R) is not fed to the switch 226R over thevideo period 52. Hence, during the video period 52, the voltage storedin the clamp capacitor 28R during the clamp period 50R is applied to theinverting input 102R of the differential amplifier 214R. The G signal,like the R signal, is fed from the differential amplifier 214G to thesample and hold circuit 216 and then to the ADC 218 to be converted to10-bit digital data. The 10-bit digital data is applied to the gammacorrection circuit 34 over the bus 114. Further, the B signal from thedifferential amplifier 214B is routed through the ADC 218 and bus 114 tothe gamma correction circuit 34.

As shown in FIG. 6C, the 1 H period including the clamp period 50R isfollowed by a clamp period 50G meant for the G signal. In the clampperiod 50G, only the G signal is clamped by the color separation signalSP_(G) and clamp signal CP_(G) from the signal generating circuit 10 inthe same manner as in the clamp period 50R. During a video signal 52following the period 50G, the G signal is amplified on the basis of acorrection voltage generated during the period 50G. Subsequently, asshown in FIG. 6D, the B signal is clamped during a clamp period 50Bwhile a correction voltage is generated. During a video period 52following the clamp period 50B, the G signal is amplified by thecorrection voltage. It is to be noted that the correction voltage meantfor the R signal is continuously held by the clamp capacitor 28R untilthe B signal clamp period 50 and subsequent video period 52 expire.Stated another way, this embodiment clamps each of the three colorsignals R, G and B every 3 H period.

By the above procedure, the R, G and B signals substantially free fromoffset components are applied to the input 206 of the ADC 218. Thesecolor signals are sequentially converted to 10-bit digital data by theADC 218. The digital R, G and B data are sequentially subjected to gammacorrection by the gamma correction circuit 34 and then written into amemory card, not shown, by way of various kinds of signal processing.

As stated above, in the illustrative embodiment, a particular feedbackclamp circuit matching one of the multiplexed R, G and B signals isactivated to store a correction voltage in the associated clampcapacitor 28. The differential amplifier 214 amplifies the input colorsignal on the basis of the correction voltage. During the next clampperiod 50, another feedback clamp circuit matching another color signalis activated to clamp the color signal. In this manner, the differentialamplifiers 214 correct offsets among the color signals on the basis ofthe color-by-color correction signals. Sequentially clamping the colorsignals during different clamp periods assigned thereto as stated aboveis successful in bringing offset components among the color signals tocoincidence with accuracy and without resorting to adjustment. Thisinsures the accurate registration of the color components. Particularly,in the processing to be executed by the gamma correction circuit 20, thecolor balance of video data lying in a comparatively low luminance rangeis improved to prevent color reproducibility from being degraded. It isnot necessary for the operator of the equipment to manipulate a videosignal inputting circuit for the accurate adjustment of offsetcorrection. Moreover, since the offset correction and level correctionare executed before the digitization of the color signals, theresolution and, therefore, the dynamic range available with the ADC 18can be used to the full extent. This leads to the improvement in thereproducibility of an image.

In this embodiment, the signal generating circuit 10 generates the colorseparation signals SP_(R), SP_(G) and SP_(B) each going high insynchronism with the clamp period 50 meant for the associated colorsignal, as shown in FIGS. 6E-6G. Alternatively, as shown in FIGS. 7A-7F,the circuit 10 may be so constructed as to sequentially generate colorseparation signals SP_(R), SP_(G) and SP_(B) each going high at aninterval in the clamp period 50 of the associated color signal; thesignals SP_(R), SP_(G) and SP_(B) turn on and turn off the switches 32R,32G and 32B, respectively. In such a case, the capacitor 234 of thesample and hold circuit 216 will hold the voltage stored therein duringthe interval between the successive color separation signals.

In the previously described two embodiments, a plurality of colorsignals are also multiplexed for one line circuit and then digitized.The clamp level data are detected out of the digital video signals colorby color to thereby produce correction data for correcting offsets.Offsets among the color signals are substantially eliminated on thebasis of the correction data. This is also successful in cancellingcolor deviation components included in the data of the video signals.Especially, the color balance of video data lying in a comparatively lowluminance range is improved to prevent color reproducibility from beingdegraded. Moreover, it is not necessary for the operator of theequipment to manipulate a video signal inputting circuit for theaccurate adjustment of offset correction.

In summary, it will be seen that the present invention provides videosignal offset cancelling circuitry which extracts data of digitizedcolor signals, produces a mean value of the clamp levels of each data,and then corrects offsets among the color signals. The circuitry,therefore, successfully cancels the deviations of the reference levelsof the color signals. Further, the circuitry of the inventionsequentially clamps the color signals every clamp period to cause theoffsets of the color signals to coincide. This is also successful incancelling the deviation of the reference levels of the color signals.Hence, in gamma correction to follow, the color balance of video datalying in a comparatively low luminance range is improved to preventcolor reproducibility from being degraded. In addition, it is notnecessary for the operator of the equipment to manipulate a video signalinputting circuit for the accurate adjustment of offset correction.

While the present invention has been described with reference to theparticular illustrative embodiments, it is not to be restricted by theembodiments but only by the appended claims. It is to be appreciatedthat those skilled in the art can change or modify the embodimentswithout departing from the scope and spirit of the present invention.

What is claimed is:
 1. An offset cancelling circuit for correctingoffsets in reference levels of a plurality of video signals fed fromimage pick-up means, each of the video signals being associated with arespective color, the offset cancelling circuit comprising:signalgenerating means for generating color separation pulses in synchronismwith a reference clock generated by said signal generating means and forgenerating clamp pulses and clock pulses in synchronism with black-outperiods of the video signals; multiplexing means for multiplexing thevideo signals from the image pick-up means into serial video signals inresponse to said color separation pulses from said signal generatingmeans, clamping said serial video signals in response to said clamppulses from said signal generating means, and converting said clampedvideo signals to produce digital video signals; video signal detectingmeans for detecting, in response to said clamp pulses from said signalgenerating means, said digital video signals of respective colors; meanvalue calculating means for calculating a mean value of clamp levels ofeach of said digital video signals detected by said video signaldetecting means, and for sequentially selecting the mean values viaselector means in response to said color separation pulses from saidsignal generating means; and correcting means for correcting the offsetsamong the video signals on the basis of said mean values.
 2. The offsetcancelling circuit as claimed in claim 1, wherein said correcting meanscomprises calculating means for subtracting a mean value from anassociated one of the video signals.
 3. The offset cancelling circuit asclaimed in claim 1, wherein said correcting means comprises:a pluralityof amplifying means each being associated with a respective one of thevideo signals for correcting a DC level of the respective video signalin response to a DC voltage applied to a control input; a plurality ofcorrection data generating means each being associated with a respectiveone of the video signals for generating correction data from the meanvalue for correcting the offset of the respective video signal; aplurality of converting means each being associated with a respectiveone of the video signals for converting the correction data of therespective video signal to an analog voltage; and a plurality offeedback means each being associated with a respective one of the videosignals for feeding back the analog voltage of the respective videosignal to the control input of an associated one of said plurality ofamplifying means as the DC voltage.
 4. The offset cancelling circuit asclaimed in claim 3, wherein said multiplexing means multiplexes thevideo signals amplified by said plurality of amplifying means into saidserial video signals.
 5. The offset cancelling circuit as claimed inclaim 4, wherein said multiplexing means comprises digitizing means forconverting said serial video signals into the digital video signals. 6.An offset cancelling circuit for correcting differences in referencelevels of a plurality of video signals each being associated with arespective color, the offset cancelling circuit comprising:a pluralityof amplifying means each being associated with a respective one of thevideo signals for correcting a DC level of the respective video signalin response to a respective DC voltage applied to a control input;multiplexing means for sequentially selecting and multiplexing the videosignals amplified by said plurality of amplifying means to output serialvideo signals; voltage generating means for generating a referencevoltage which constitutes a target for voltages of said serial videosignals outputted by said multiplexing means; a plurality of feedbackmeans each being associated with a respective one of the video signalsfor clamping the voltage of a respective serial video signal outputtedby said multiplexing means not lying in a video period to produce therespective DC voltage matching a difference between the voltage of therespective serial video signal and said reference voltage; and aplurality of voltage storing means each being associated with arespective one of the video signals for storing the respective DCvoltage until the next serial video signal of corresponding colorarrives and for applying the respective DC voltage to said control inputof a respective one of said plurality of amplifying means.
 7. The offsetcancelling circuit as claimed in claim 6, wherein said multiplexingmeans comprises sampling and holding means for sampling and temporarilyholding the video signals outputted by said plurality of amplifyingmeans.
 8. The offset cancelling circuit as claimed in claim 6, furthercomprising:means for driving one of said plurality of feedback means ata time; and means for driving said multiplexing means such that one ofthe video signals corresponding to said one of said plurality offeedback means is outputted from said multiplexing means as said serialvideo signal.
 9. The offset cancelling circuit as claimed in claim 8,further comprising means for driving said multiplexing meanscontinuously.
 10. The offset cancelling circuit as claimed in claim 8,further comprising means for driving said multiplexing meansintermittently.